Over the past five years, NAND flash has gone from an exceedingly expensive storage solution that only a handful of customers could afford to a mainstream product used by millions of high-speed storage devices. This shift has been great for consumers and materially impacted the performance of even older systems, but NAND flash has long-term scaling and reliability issues. Researchers across the world have continued searching for alternative storage mediums that can store data for longer periods of time and use less power to perform read/write sequences.
One of these alternatives is called Ferroelectric RAM, or FeRAM for short. Like DRAM, FeRAM changes state when an electrical charge is applied. The difference between the two is that DRAM has to be continually recharged — FeRAM doesn’t. Applying an electrical field to an FeRAM cell causes a shift in the structure’s polarity that remains until another field is applied. FeRAM is faster than NAND flash and draws less power for write cycles — but up until now, there’s always been a major catch.
The only way to read FeRAM cell states is to force the cells into one position (0 or 1) and take note of how the polarity in each cell shifted. If data is stored in an array as 0,0,1,1,1, and an electrical field is applied to change all the cells to read “0,” only the last three cell values will change — but the act of reading the data destroys the stored value. There’s no such thing as a “read” cycle using conventional FeRAM, just read-write cycles. This slows system performance and impacts overall reliability.
Now, a research team from UC Berkeley has demonstrated a type of FeRAM that avoids the destructive read problem. FeRAM built from bismuth ferrite (BiFeO3) exhibits an unusual property — it gives off voltage when struck by light. Critically, the voltage values released depend on the polarity of the cell. If a cell with a “0″ value releases a voltage of x and a cell with a “1″ value releases a voltage of y, it’s possible to read the stored values without needing to rewrite them afterwards.
According to the research team, it takes roughly 10 nanoseconds to perform read/write operations from this type of FeRAM at 3.3V. NAND Flash takes significantly longer (how long depends on the type of NAND) and draws 10-15V for the same operation. That’s a definite advantage for FeRAM — if certain other roadblocks can be conquered. The authors acknowledge that building FeRAM cells with non-destructive read capability requires that each cell be illuminated with its own light source. These prototype tests were conducted on cell arrays a full 10 micrometers in size — that’s the equivalent of 10,000 nanometers. Current NAND flash is being built at ~20nm.
Storage densities, in other words, remain an enormous problem. It’s not clear if that’s a problem that FeRAM can overcome; materials tend to lose ferroelectric properties at small sizes and any optical array for non-destructive reads would need to scale to equivalent nanometer size. The research team at UC Berkeley used an array of light to illuminate more than one cell at a time, which also improves power efficiency — individual light sources would inevitably add to the power cost of read/write operations.
Why it matters
NAND flash is running out of steam. Manufacturers have begun adopting “soft” product labels; denoting a product line as being built on “1X” rather than a hard process node due to scaling concerns. Sandisk recently acknowledged that its “1Y” flash, for example, is built on the same node as “1X.” As we’ve discussed before, this isn’t a problem unique to any manufacturer; it’s a fundamental problem with the laws of physics. As we approach atomic scales, the difficulty of building a CMOS transistor skyrockets and the value of new nodes plunges.
3D NAND is seen as a way to improve chip densities and drive lower prices without necessarily moving to new process nodes. GlobalFoundries and TSMC are both moving to blended process nodes that pair 20nm front-ends with lower-node backend work. But in the long run, we need different structures that can continue scaling where conventional silicon is failing. Ferroelectric RAM may or may not prove to be a successor to flash memory, but the ongoing work in these areas is what will ultimately enable post-CMOS scaling.